extended deadline model

git-svn-id: https://www.prismmodelchecker.org/svn/prism/prism/trunk@852 bbc10eb1-c90d-0410-af57-cb519fbb1720

prism-examples/firewire/impl/deadline.nm

@@ -17,25 +17,27 @@ const int rc_fast_min = 76;
 // for slow
 const int rc_slow_max = 167;
 const int rc_slow_min = 159;
-// for wire
-const int delay = 36;
+// wire
+const int delay;
+// probability of chooisng fast
+const double fast;
+const double slow=1-fast;
 
 module wire12
 	
-	// local state
-	w12 : [0..9];
+	w12 : [0..10];
 	// 0 - empty
-	// 1 - rec_req
-	// 2 - rec_req_ack
-	// 3 - rec_ack
-	// 4 - rec_ack_idle
-	// 5 - rec_idle
-	// 6 - rec_idle_req
-	// 7 - rec_ack_req
-	// 8 - rec_req_idle
-	// 9 - rec_idle_ack
-
-	// clocks for wire12
+	// 1 -	rec_req
+	// 2 -  rec_req_ack
+	// 3 -	rec_ack
+	// 4 -	rec_ack_idle
+	// 5 -	rec_idle
+	// 6 -	rec_idle_req
+	// 7 -	rec_ack_req
+	// 8 -	rec_req_idle
+	// 9 -	rec_idle_ack
+	
+	// clock for wire12
 	y1 : [0..37];
 	y2 : [0..37];
 	
@@ -95,7 +97,6 @@ module node1
 
 	// clock for node1
 	x1 : [0..168];
-	
 	// local state
 	s1 : [0..8];
 	// 0 - root contention
@@ -109,13 +110,12 @@ module node1
 	// 8 - almost_child
 	
 	// added resets to x1 when not considered again until after rest
-	// removed root and child (using almost root and almost child)
 	
 	// root contention (immediate state)
-	[snd_idle12] (s1=0) -> 0.5 : (s1'=2) & (x1'=0) +  0.5 : (s1'=3) & (x1'=0);
+	[snd_idle12] (s1=0) -> fast : (s1'=2) & (x1'=0) +  slow : (s1'=3) & (x1'=0);
 	[rec_idle21] (s1=0) -> (s1'=1);
 	// rec_idle (immediate state)
-	[snd_idle12] (s1=1) -> 0.5 : (s1'=4) & (x1'=0) +  0.5 : (s1'=5) & (x1'=0);
+	[snd_idle12] (s1=1) -> fast : (s1'=4) & (x1'=0) +  slow : (s1'=5) & (x1'=0);
 	[rec_req21]  (s1=1) -> (s1'=0);
 	// rec_req_fast
 	[rec_idle21] (s1=2) -> (s1'=4);
@@ -139,9 +139,13 @@ module node1
 	[rec_req21] (s1=6) -> (s1'=0);
 	[rec_ack21] (s1=6) -> (s1'=8);
 	[time]      (s1=6) -> (s1'=s1);
-	// loop in final states to remove deadlock (but wait until both process have decided)
+	// almost root (immediate) 
+	// loop in final states to remove deadlock
+	// (wait until both process have decided otherwise need fairness)
 	[] (s1=7) & (s2=8) -> (s1'=s1);
 	[time] (s1=7) -> (s1'=s1);
+	[] (s1=8) & (s2=7) -> (s1'=s1);
+	[time] (s1=8) -> (s1'=s1);
 	
 endmodule